Digital electronic circuit for use in implementing digital logic functions

ABSTRACT

A digital electronic circuit having first and second sections. The first section is adapted to transmit one of N input signals. The second section is adapted to receive the signal transmitted by the first section and one or more control signals. The second section is configured to output either an inverse of the signal transmitted by the first section or a logical 0, or to output either an inverse of the signal transmitted by the first section or a logical 1. The second section also may be selectively configurable.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a continuation of U.S. patent applicationSer. No. 09/477,153, filed Jan. 4, 2000 of Dzung Joseph Tran and Mark W.Acuff for DIGITAL ELECTRONIC CIRCUIT FOR USE IN IMPLEMENTING DIGITALLOGIC FUNCTIONS, now U.S. Pat. No. 6,288,593 and U.S. patent applicationSer. No. 09/939,348, filed Aug. 24, 2001 of Dzung Joseph Tran and MarkW. Acuff for DIGITAL ELECTRONIC CIRCUIT FOR USE IN IMPLEMENTING DIGITALLOGIC FUNCTIONS.

FIELD OF THE INVENTION

[0002] The present invention relates to digital electronics, and moreparticularly to a digital electronic circuit for use in logic design.

BACKGROUND

[0003] Digital electronic circuits are used in virtually every modemelectronic system, such as computers, watches and telephones. Undercontinuous pressure from users for increased functionality fromelectronic systems, designers and manufacturers of digital electroniccircuits constantly strive to reduce the size and increase theperformance of their circuits. Even modest gains in the density and/orperformance of a circuit become substantial if the circuit is repeatedmany times within a system.

[0004] Traditionally, digital logic functions have been implemented witha plurality of discrete logic circuits or gates including AND gates, ORgates, NAND gates, NOR gates, etc., each constructed of severaltransistors. Subsequently, it was discovered that certain specialpurpose digital circuits such as multiplexers could be used to implementdigital logic functions using fewer transistors than with discretegates. In addition, improved multiplexers were developed which used evenfewer transistors. These multiplexers, commonly known as “TransmissionGate” multiplexers, are described in my prior U.S. Pat. Nos. 5,040,139,5,162,666, 5,200,907, and 5,548,231, the disclosures of which are hereinincorporated by reference.

[0005]FIG. 1 shows an exemplary 4:1 transmission gate multiplexer 10connected to an output driver 11. Transmission gate multiplexer 10includes three 2:1 transmission gate multiplexers 12 a-c connected in aserial cascading or hierarchical configuration, as described in my U.S.Pat. No. 5,162,666. The 2:1 transmission gate multiplexer (hereinafterreferred to as a TGM) is the basic building block of larger transmissiongate multiplexer systems. Each TGM is configured to receive two inputsignals I_(i) and I_(i+1), and a control signal S_(i). The TGM selectsone of the two input signals based on the logic value of control signalS_(i). The selected input signal is transmitted to the output of theTGM, while the input signal not selected is blocked. The output of eachTGM is connected to one of the inputs of the next higher TGM until finalTGM 12 c is reached. Thus, one of N input signals can be selected fortransmission using N−1 TGM's connected in a hierarchical arrangement.The output of final TGM 12 c typically is connected to an output driver11 which is adapted to charge and discharge relatively large capacitiveloads. The signal from output driver 11 is designated Q in FIG. 1.

[0006]FIG. 2 shows the construction of a typical TGM and output driverusing Complimentary Metal Oxide Semiconductor (CMOS) technology. TGM 12c includes two transmission gate pairs 16, each having one P-channeltransistor 18 with a drain 20, a source 22, and a gate 24, and oneN-channel transistor 26 with a drain 28, a source 30, and a gate 32. Thedrain of each P-channel transistor is connected to the source of thecorresponding N-channel transistor. Similarly, the source of eachP-channel transistor is connected to the drain of the correspondingN-channel transistor.

[0007] The P-channel transistor will transmit a signal between thesource and drain only when a negative voltage is applied to the gatewith respect to the source. In contrast, the N-channel transistor willtransmit a signal between the source and drain only when a positivevoltage is applied to the gate with respect to the source. Thus, ifopposite voltages are applied to the gates of the P-channel andN-channel transistor simultaneously, both transistors will either beswitched “on” or switched “off.”

[0008] A select signal S_(i) is connected to the P-channel transistor ofthe first transmission gate pair and the N-channel transistor of thesecond transmission gate pair. The select signal is also passed throughan inverter 34 which produces a signal opposite the select signal.Inverter 34 may be a conventional CMOS transistor pair connected betweenVDD and Ground, as is described in more detail below. The invertedselect signal is connected to the N-channel transistor of the firsttransmission gate pair and the P-channel transistor of the secondtransmission gate pair. As a result, when S_(i) is low (also referred toherein as “Ground” or “logical 0”) the input signal I_(i) connected tothe first transmission gate pair is transmitted to the output node 36 ofthe TGM. Conversely, when S_(i) is high (also referred to herein as“VDD” or “logical 1”) the input signal I_(i+1) connected to the secondtransmission gate pair is transmitted to output node 36.

[0009] The transmitted signal at output node 36 is connected to anoutput driver 11. Similar to inverter 34, the exemplary output drivershown in FIG. 2 is in the form of a CMOS inverter having one P-channeltransistor 38 and one N-channel transistor 40. The P-channel transistoris connected between VDD and the N-channel transistor, while theN-channel transistor is connected between Ground and the P-channeltransistor. The output node of the TGM is connected to the gates oftransistors 38 and 40. The inverter output node 42 produces a signal Qopposite the transmitted signal. Transistors 38 and 40 are appropriatelysized to drive the expected output load. As can be seen from FIG. 2, thecombination of the final TGM and output driver uses eight transistors.If desired, the output driver may include two inverters connected inseries to produce the transmitted signal without inversion.

[0010] In addition to the exemplary multiplexer described above, thereare many other multiplexer configurations well known in the art. Forexample an N:1 multiplexer can be formed by arranging a plurality ofTGM's in a tree-type hierarchical structure as is known in the art. Asanother example, multiplexers can be formed using traditional logicgates instead of transmission gates. In view of the wide-spread use ofmultiplexers to implement digital logic functions, an increase inmultiplexer performance or a reduction in the number of transistorsneeded to form a multiplexer would constitute a substantial improvementover existing technology.

SUMMARY

[0011] The invention includes a digital electronic circuit for use inimplementing digital logic functions. The invented circuit has first andsecond sections. The first section is adapted to transmit one of N inputsignals, and in some embodiments is a configuration of serial cascadedTGMs. The second section is adapted to receive the signal transmitted bythe first section and one or more control signals. Additionally, thesecond section is configured to output either an inverse of the signaltransmitted by the first section or a constant logic value in responseto the one or more control signals. For example, in one embodiment thesecond section is adapted to output either an inverse of the signaltransmitted by the first section or a logical 0. In another embodiment,the second section is adapted to output either an inverse of the signaltransmitted by the first section or a logical 1. The second section alsomay be selectively configurable in either of these configurations. Inone exemplary embodiment, the second section includes no more than sixCMOS transistors. In another exemplary embodiment, the second sectionincludes no more than four CMOS transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a schematic of an exemplary serial cascaded 4:1TGM-based multiplexer with associated output driver, as is known in theart.

[0013]FIG. 2 is a schematic of an exemplary TGM and output driver, as isknown in the art. The circuit shown in FIG. 2 corresponds to the portionof the multiplexer of FIG. 1 within the dashed lines.

[0014]FIG. 3 is a schematic of a configurable circuit according to thepresent invention.

[0015]FIG. 4 is a schematic of the circuit of FIG. 3 configured tooutput either an inverse of a signal transmitted by a multiplexer or alogical 0 in response to two control signals.

[0016]FIG. 5 is a schematic of the circuit of FIG. 3 configured tooutput either an inverse of a signal transmitted by a multiplexer or alogical 1 in response to two control signals.

[0017]FIG. 6 is a schematic of the circuit of FIG. 3 configured tooutput either an inverse of a signal transmitted by a multiplexer or alogical 0 in response to one control signal.

[0018]FIG. 7 shows another configuration of the invention.

[0019]FIG. 8 is a schematic of the circuit of FIG. 3 configured tooutput either an inverse of a signal transmitted by a multiplexer or alogical 1 in response to one control signal.

[0020]FIG. 9 shows another configuration of the invention.

[0021]FIG. 10 shows an invented central processing unit.

DETAILED DESCRIPTION

[0022] A digital electronic circuit for use in multiplexer-implementedlogic is indicated generally at 50 in FIG. 3. Circuit 50 includes afirst section 52 adapted to transmit one of N input signals, and asecond section 54 associated with the first section. Second section 54may take various configurations. In some configurations, second section54 is adapted to output either an inverse of the signal transmitted bythe first section or a logical 0 in response to one or more controlsignals. In other configurations, second section 54 is adapted to outputeither an inverse of the signal transmitted by the first section or alogical 1, in response to one or more control signals. The secondsection also may be made to be selectively configurable in one of thevarious configurations. In one exemplary application, second section 54may be used to replace the final stage and output driver of amultiplexer logic circuit.

[0023] First section 52 is shown in FIG. 3 as an N:1 serial cascademultiplexer, such as depicted in FIGS. 1-2 and described above, but itmay be any other circuit adapted to receive a plurality of input signalsand to transmit a selected one of the plural input signals, such as abinary tree multiplexer or some other circuit. FIGS. 4-9 show firstsection 52 in block form to represent a N:1 serial cascade multiplexeras well as other circuits adapted to receive a plurality of inputsignals and to transmit a selected one of the plural input signals.Preferably first section 52 is a serial cascaded TGM multiplexer. Wherefirst section 52 is a multiplexer, it typically will include N inputsignal nodes 56, each adapted to receive one of the N input signalsI₁-I_(N). For example, first section 52 may be a 2:1 multiplexer, or a3:1 multiplexer, or a 4:1 multiplexer, or a 5:1 multiplexer, etc. Firstsection 52 also may include one or more additional input or select nodes58, adapted to receive one or more select signals. When first section 52is a set of serial cascaded TGMs, having N inputs, the first sectionwill include N-1 select signals, each of which goes to only one TGM andeach of which is logically independent. First section 52 is adapted totransmit a selected one of the input signals I_(i), depending on thevalue(s) of the one or more select signals, to output node 60.

[0024] Second section 54 includes a first P-channel/N-channel transistorpair (P1/N1) controllable by a first control signal X, and a secondP-channel/N-channel transistor pair (P2/N2) controllable by a secondcontrol signal Y. Second section 54 also includes a thirdP-channel/N-channel transistor pair (P3/N3) controllable by the signal11 transmitted from the first section 52. The third P-channel/N-channeltransistor pair function as an inverting output driver or output meansfor first section 52. The first and second P-channel/N-channeltransistor pairs are interconnectable with the third P-channel/N-channeltransistor pair, and function as a control means to either enable ordisable the output driver in response to one or more control signals.When the output driver is disabled, thereby preventing transmission ofthe signal from first section 52, the second section outputs a constantlogic value depending on its configuration. As used herein, the outputdriver is disabled when it cannot output one or more signals. Forexample, the output driver is disabled, as used herein, when it cannotoutput a logical 0, even if it can output a logical 1, or vice versa.

[0025] Thus, second section 54 functions similar to the combination of afinal multiplexing stage (e.g., TGM 12 c) and an output driver (e.g.,output driver 11) by selecting between the output of the previousmultiplexing stages and a separate logic value. However, a typical finalmultiplexing stage as described above selects between the output ofprior stages and a separate value that is variable and determined by afinal input signal. In contrast, second section 54 selects between theoutput of prior stages and a separate value that is constant anddetermined by the configuration of the second section rather thanselecting between the output of prior stages and another variable inputsignal.

[0026] Second section 54 replaces the final multiplexing stage (thefinal TGM in a serial cascade multiplexer) and output driver. Replacingthe final stage of a serial cascade TGM multiplexer and its associatedoutput driver with a second section adapted to output a constant valuerather than a input signal that is variable, although counter-intuitivebecause it reduces the number of variable inputs, does not limit theapplicability of a circuit using second section 54. In fact, virtuallyany arbitrary digital logic function can be implemented with a suitablefirst section 52 connected to a second section 54 with fewer transistorsthan otherwise would be required. This is demonstrated by the followingsimple example.

[0027] Assume a digital logic designer wishes to implement an arbitrarythree-variable function A=f(X1, X2, X3), where A can be expressed by thefollowing truth table: X₁ X₂ X₃ A 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 01 1 0 1 0 1 1 0 0 1 1 1 0

[0028] This truth table can be reduced to the following, where thesymbol {overscore (X₃)} represents the logical inverse or opposite ofsignal X₃: X₁ X₂ A 0 0 {overscore (X₃)} 0 1 X₃ 1 0 {overscore (X₃)} 1 10

[0029] Function A can be implemented with a 2:1 multiplexer firstsection that selects between the input signals X₃ and {overscore (X₃)}depending on a select signal X₂, and a second stage that outputs alogical 0 when control signals X1 and X2 are each a logical 1.

[0030] Returning attention to FIG. 3, second section 54 is shown priorto being configured for operation. First P-channel transistor P1includes a drain 62 and a source 64, which is connected to VDD. As usedherein VDD represents a voltage level with respect to Ground suitablefor the selected circuit technology. For example, where circuit 50 isconstructed using CMOS technology, typical voltage levels for VDDinclude 5-volts, 2.5-volts, etc. However, it will be appreciated thatthe voltage level selected for VDD may vary depending on the applicationand changing circuit dimensions, and that circuit 50 is not limited toany particular voltage levels for VDD. In any event, first P-channeltransistor P1 also includes a gate 66 connected to a first controlsignal node 68. Second P-channel transistor P2 includes a drain 70, asource 72 connected to drain 62 of transistor P1, and a gate 74connected to a second control signal node 76. Drain 70 of transistor P2is not connected when second section 54 is in an “unconfigured” state.

[0031] First N-channel transistor N1 includes a drain 78, a source 80connected to Ground, and a gate 82 connected to first control signalnode 68. Second N-channel transistor N2 includes a drain 84, a source 86connected to drain 78 of transistor N1, and a gate 88 connected tosecond control signal node 76. Drain 84 of transistor N2 is notconnected when second section 54 is in an “unconfigured” state.

[0032] Third P-channel transistor P3 includes a source 90, a drain 92,and a gate 94 connected to first section output node 60. Third N-channeltransistor N3 includes a source 96, a drain 98 connected to drain 92 oftransistor P3, and a gate 100 connected to first section output node 60.In addition, drain 92 of transistor P3 and drain 98 of transistor N3 areconnected to a second section output node 102. Source 90 of transistorP3 and source 96 of transistor N3 are not connected when second section54 is in an “unconfigured” or “selectively configurable” state.

[0033] Although shown in an unconfigured state in FIG. 3, second section54 is configurable in any of a plurality of configurations byselectively interconnecting the transistors as described below.Typically, the second section will be configured to produce the desiredlogical function from a selected number of input and/or control signals.It will be appreciated that circuit 50 can be used in a variety of ways.For example, circuit 50 may be constructed in its unconfigured state asan application specific integrated circuit (ASIC) which is thenselectively configured by interconnecting the transistors of the secondsection through a final metallization layer. As another example, circuit50 can be used in digital logic design as a selectively configurablecircuit layout cell which can be used to generate arbitrary logicfunctions. As another example, circuit 50 can be constructed as aprogrammable logic array (PLA) with fusible interconnections between thetransistors of second section 54. In this latter example, a user canselectively configure the circuit by burning, melting, etc., theunwanted connections.

[0034] Additionally, the various configurations of circuit 50, whichwill be described in more detail below, can be constructed separately toachieve the desired logic function in place of the multiplexer arraysdescribed above. The various configurations preferably are formed asintegrated circuits with first section 52 and second section 54 on asingle substrate. This allows the circuit to perform faster and withless power dissipation than circuits that achieve similar logicfunctions through multiple, deserete integrated circuits. This alsoallows the circuit to have a smaller physical size or area. Theconfigurations may be formed on the single substrate as a centralprocessing unit (CPU) and/or with other circuitry, as would be known bya person of ordinary skill in the art. A single semiconductor substrate51 showing the invention as a CPU is shown in FIG. 10.

[0035]FIG. 4 depicts circuit 50 in which the transistors of secondsection 54 are interconnected to form a first configuration. As shown,second section 54 is configured in the first configuration by connectingdrain 62 of transistor P1 to source 90 of transistor P3, connectingdrain 70 of transistor P2 to VDD, connecting drain 84 of transistor N2to second section output node 102, and connecting source 96 oftransistor N3 to Ground.

[0036] When at least one of control signal X or Y is a 0, then at leastone of transistor P1 or P2 will be switched on, respectively. Thus,source 90 of transistor P3 will be connected to VDD. In addition, atleast one of transistor N1 or N2 will be switched off, isolating outputnode 102 from Ground. Since source 96 of transistor N3 is connected toGround, the output driver formed by transistors P3 and N3 is enabled andoutputs to output node 102 the inverse of the signal transmitted byfirst section 52.

[0037] Conversely, when both control signals X and Y are a 1, then bothtransistors P1 and P2 will be switched off, isolating source 90 oftransistor P3 from VDD. The P3/N3 output driver is therefore disabled(i.e., it cannot output a logical 1 even though it can output a logical0) and the signal transmitted by the first section is blocked. However,both of transistors N1 and N2 will be switched on, connecting outputnode 102 to Ground. It will be appreciated that the logical functionperformed by second section 54 in the first configuration can beexpressed by the Boolean equation Q={overscore (I+XY)}, where Q is theoutput signal of circuit 50 at output node 102, and I is the signaltransmitted by first section 52 to output node 60.

[0038] The logical function performed by second section 54 in the firstconfiguration can also be expressed by a truth table. For example, wherefirst section 52 is a 2:1 multiplexer adapted to transmit one of twoinput signals I₁, I₂ depending on a select signal S, the output signal Qat output node 102 can be expressed by: S X Y Q 0 0 0 {overscore (I₁)} 00 1 {overscore (I₁)} 0 1 0 {overscore (I₁)} 0 1 1 0 1 0 0 {overscore(I₂)} 1 0 1 {overscore (I₂)} 1 1 0 {overscore (I₂)} 1 1 1 0

[0039] As demonstrated by the Boolean equation and truth table above,second section 54 is configurable to replace the final stage and outputdriver in a multiplexer logic circuit in which the output of the circuitis a constant 0 for a particular combination of input, select, and/orcontrol signals. Furthermore, second section 54 achieves this functionwith no more than six CMOS transistors (three P-channel/N-channeltransistor pairs). In contrast, the final stagehand output driver shownin FIG. 2 use at least eight transistors. It will be understood by thoseof skill in the art that this 25% reduction in the number of transistorsleads to substantial improvements in circuit density, propagation delay,power dissipation, etc.

[0040] Turning now to FIG. 5, the transistors of second section 54 areshown interconnected to form a second configuration. Second section 54is configured in the second configuration by connecting drain 70 oftransistor P2 to second section output node 102, connecting drain 84 oftransistor N2 to Ground, connecting source 90 of transistor P3 to VDD,and connecting source 96 of transistor N3 to drain 78 of transistor Ni.

[0041] When at least one of control signal X or Y is a 1, then at leastone of transistor N1 or N2 will be switched on, respectively. Thus,source 96 of transistor N3 will be connected to Ground. In addition, atleast one of transistor P1 or P2 will be switched off, isolating outputnode 102 from VDD. Since source 90 of transistor P3 is connected to VDD,the output driver formed by transistors P3 and N3 is enabled and outputsto output node 102 the inverse of the signal transmitted by firstsection 52.

[0042] Conversely, when both control signals X and Y are a 0, then bothtransistors N1 and N2 will be switched off, isolating source 96 oftransistor N3 from Ground. The P3/N3 output driver is therefore disabled(i.e., it cannot output a logical 0 even though it can output alogical 1) and the signal transmitted by the first section is blocked.However, both of transistors P1 and P2 will be switched on, connectingoutput node 102 to VDD. It will be appreciated that the logical functionperformed by second section 54 in the second configuration can beexpressed by the Boolean equation Q={overscore (I(X+Y))}, where Q is theoutput signal of circuit 50 at output node 102, and I is the signaltransmitted by first section 52 to output node 60.

[0043] The logical function performed by second section 54 in the secondconfiguration can also be expressed by a truth table. For example, wherefirst section 52 is a 2:1 multiplexer adapted to transmit one of twoinput signals I₁, I₂ depending on a select signal S, the output signal Qat output node 102 can be expressed by: S X Y Q 0 0 0 1 0 0 1 {overscore(I₁)} 0 1 0 {overscore (I₁)} 0 1 1 {overscore (I₁)} 1 0 0 1 1 0 1{overscore (I₂)} 1 1 0 {overscore (I₂)} 1 1 1 {overscore (I₂)}

[0044] Thus, second section 54 is configurable to replace the finalstage and output driver in a multiplexer logic circuit in which theoutput of the circuit is a constant 1 for a particular combination ofinput, select, and/or control signals. As with the first configuration,second section 54 achieves this function with no more than six CMOStransistors (three P-channel/N-channel transistor pairs). Furthermore,second section 54 is selectively configurable in either the first orsecond configurations as required for a particular application.

[0045] As shown in FIG. 6, second section 54 is also selectivelyconfigurable in a third configuration. Similar to the firstconfiguration, second section 54 outputs either an inverse of the signaltransmitted by first section 52 or a logical 0 when configured in thethird configuration. However, the third configuration is different thaneither the first or second configurations. The second section isconfigured in the third configuration by connecting drain 62 oftransistor P1 to source 90 of transistor P3, connecting drain 78 oftransistor N1 to second section output node 102, and connecting source96 of transistor N3 to Ground.

[0046] The drains of transistors P2 and N2 are not connected when thesecond section is in the third configuration. Thus, transistors P2 andN2 are inoperative. To prevent parasitic effects due to floatingvoltages, second control signal node 76 typically is connected either toVDD or to Ground. Alternatively, transistors P2 and N2 and control node76, may be omitted from second section 54 so that second section 54 usesno more than four CMOS transistors (two P-channel/N-channel transistorpairs), as shown in FIG. 7.

[0047] When control signal X is a 1, transistor P1 is switched off,isolating source 90 of transistor P3 from VDD. The output driver formedby transistors P3 and N3 is therefore disabled (i.e., it cannot output alogical 1 even though it can output a logical 0) and the signaltransmitted by the first section is blocked. However, transistor N1 isswitched on, connecting output node 102 to Ground. Conversely, whencontrol signal X is a 0, transistor P1 is switched on, connecting source90 of transistor P3 to VDD. In addition, transistor N1 is switched off,isolating output node 102 from Ground. Since source 96 of transistor N3is connected to Ground, the P3/N3 output driver is enabled and outputsthe inverse of the signal transmitted by first section 52 to output node102.

[0048] It will be appreciated that the logical function performed bysecond section 54 in the third configuration can be expressed by theBoolean equation Q={overscore (I+X)}, where Q is the output signal ofcircuit 50 at output node 102, and I is the signal transmitted by firstsection 52 to output node 60. The logical function performed by secondsection 54 in the third configuration can also be expressed by a truthtable. For example, where first section 52 is a 2:1 multiplexer adaptedto transmit one of two input signals I₁, I₂ depending on a select signalS, the output signal Q at output node 102 can be expressed as follows,where control signal Y is not used: S X Y Q 0 0 — {overscore (I₁)} 0 1 —0 1 0 — {overscore (I₂)} 1 1 — 0

[0049] Thus, second section 54 is configurable in the thirdconfiguration to output either an inverse of the signal transmitted bythe first section or a logical 0 in response to only one control signal.

[0050] Turning now to FIG. 8, it can be seen that second section 54 isselectively configurable in a fourth configuration to output either aninverse of the signal transmitted by the first section or a logical 1.The fourth configuration is different than any of the first, second, orthird configurations. The second section is configured in the fourthconfiguration by connecting drain 62 of transistor P1 to second sectionoutput node 102, connecting source 90 of transistor P3 to VDD, andconnecting source 96 of transistor N3 to drain 78 of transistor N1.

[0051] As in the third configuration, the drains of transistors P2 andN2 are not connected when the second section is in the fourthconfiguration. Thus, transistors P2 and N2 are inoperative and thesecond control signal node 76 typically is connected to either VDD orGround. Alternatively, transistors P2 and N2 and control signal node 76may be omitted from second section 54, leaving only four CMOStransistors needed to achieve the function of the second section, asshown in FIG. 9.

[0052] In any event, when control signal X is a 0, transistor N1 isswitched off, isolating source 96 of transistor N3 from Ground. Theoutput driver formed by transistors P3 and N3 is therefore disabled(i.e., it cannot output a logical 0 even though it can output alogical 1) and the signal transmitted by the first section is blocked.However, transistor P1 is switched on, connecting output node 102 toVDD. Conversely, when control signal X is a 1, transistor N1 is switchedon, connecting source 96 of transistor N3 to Ground. In addition,transistor P1 is switched off, isolating output node 102 from VDD. Sincesource 90 of transistor P3 is connected to VDD, the P3/N3 output driveris enabled and outputs to output node 102 the inverse of the signaltransmitted by first section 52.

[0053] It will be appreciated that the logical function performed bysecond section 54 in the fourth configuration can be expressed by theBoolean equation Q={overscore (IX)}, where Q is the output signal ofcircuit 50 at output node 102, and I is the signal transmitted by firstsection 52 to output node 60. The logical function performed by secondsection 54 in the fourth configuration can also be expressed by a truthtable. For example, where first section 52 is a 2:1 multiplexer adaptedto transmit one of two input signals I₁, I₂ depending on a select signalS, the output signal Q at output node 102 can be expressed as followswhere control signal Y is not used: S₁ X Y Q 0 0 — 1 0 1 — {overscore(I₁)} 1 0 — 1 1 1 — {overscore (I₂)}

[0054] Thus, second section 54 is configurable in the fourthconfiguration to output either an inverse of the signal transmitted bythe first section or a logical 1 in response to only one control signal.

[0055] A significant feature of each configuration of second section 54described above and as shown in the figures, is that the output of thesecond section is determined without feedback. In other words, secondsection output node 102 is not connected to the gate of any transistorin circuit 50, and specifically not to an input of one of the TGMs ormultiplexing stages of the first section, so the signal at output node102 is not fed back into circuit 50. This is in contrast to othercircuit designs, such as flip-flops, which use the output signal as aninput to one or more transistor gates. The use of feedback in a circuitmay slow the speed of the circuit since a feedback signal is firsttransmitted through a circuit to an output, and then returned to aninput node, and then transmitted through at least a portion of thecircuit again. This repeated transmission of a feedback signal through acircuit may cause delay in generating a final output signal. Therefore,the absence of feedback in circuit 50 maximizes the speed of thecircuit.

[0056] As discussed above, first section 52 may be any suitable circuitadapted to transmit a selected one of N input signals. For example,first section 52 may be a TGM multiplexer having one or more TGM'sconnected in a serial cascading hierarchy where the output of each TGM(except the final TGM) is connected to one of the inputs of the nexthigher TGM in the hierarchy. This particular configuration of firstsection 52 offers additional benefits over other first circuitconfigurations.

[0057] For instance, a serial cascade TGM structure minimizes internalfeedback and fan-out of the input signals by ensuring that the output ofeach TGM is connected to only one P-channel/N-channel transmission gatepair. This reduces the propagation delay of the input signals byreducing the loading on the TGM outputs. In contrast, other TGMarrangements such as EXCLUSIVE OR gates and EXCLUSIVE NOR gates areconfigured so that the output of at least one TGM is connected to aplurality of P-channel/N-channel transmission gate pairs. Similarly, theserial cascade structure ensures that each select signal drives only asingle TGM rather than multiple TGM's. This reduces the loading on theselect signal nodes, thereby decreasing propagation delay of the selectsignals. In contrast, most select signals used in tree-type hierarchicalstructures must control multiple TGM's. Thus, the minimization ofinternal feedback and fan-out and the use of individual select lines ina serial cascaded multiplexer combined with a second section asdescribed above results in a faster circuit. It also results in acircuit that has less power dissipation and that occupies less area.

[0058] As described above, circuit 50 can be used by digital logicdesigners in place of conventional multiplexer function generators.After using known techniques to determine a plurality of digital outputvalues Q, one for each combination of digital input values, the logicdesigner can select an appropriate circuit 50 having a first sectionadapted to transmit a selected one of N input signals. If necessary, thedesigner may develop a truth table (such as those described above)depicting the desired logical function, and use known techniques todetermine how to implement the function using multiplexer logic.Finally, the designer configures the second section to produce thedesired output value based on the input signals by interconnecting thetransistors of the second section as described above.

[0059] While the invention has been disclosed in its preferred forms,the specific embodiments thereof as disclosed and illustrated herein arenot to be considered in a limiting sense. Applicants regard the subjectmatter of the invention to include all novel and non-obviouscombinations and subcombinations of the various elements, features,functions and/or properties disclosed herein. The following claimsdefine certain combinations and subcombinations which are regarded asnovel and non-obvious. Other perspectives, combinations andsubcombinations of features, functions, elements and/or properties maybe claimed through amendment of the present claims or presentation ofnew claims in this or a related application. Such claims, whether theyare different, broader, narrower or equal in scope to the originalclaims, are also regarded as included within the subject matter ofapplicants' invention.

We claim:
 1. A CMOS digital electronic circuit comprising: a firstsection adapted to transmit one of N input signals; and a second sectionselectively configurable in either a first or a second configuration,wherein the second section is adapted to receive the signal transmittedby the first section and one or more control signals, and to outputeither an inverse of the signal transmitted by the first section or alogical 0 when in the first configuration, or to output either aninverse of the signal transmitted by the first section or a logical 1when in the second configuration, the output in either configurationbeing responsive to the one or more control signals, and wherein thesecond section includes no more than six transistors.
 2. The circuit ofclaim 1, wherein the output of the second section is responsive to twocontrol signals.
 3. The circuit of claim 1, wherein the output of thesecond section is responsive to one control signal.
 4. The circuit ofclaim 1, wherein the first section comprises an N:1 TGM multiplexer. 5.The circuit of claim 4, wherein the TGM multiplexer is arranged in aserial cascade structure.
 6. The circuit of claim 1, wherein the secondsection includes no more than four transistors.
 7. The circuit of claim6, wherein the first section comprises an N:1 TGM multiplexer.
 8. Thecircuit of claim 7, wherein the TGM multiplexer is arranged in a serialcascade structure.
 9. A method of digital electronic circuit design toproduce desired digital output values in response to combinations offive digital input values (I1, I2, S1, X, Y), the method comprising:deciding upon a plurality of digital output values Q, one for eachcombination of digital input values; selecting a CMOS circuit having atleast one selectively configurable section comprising no more thantwelve transistors, wherein the section includes five input signal nodesand at least one output signal node; and configuring the section tooutput Q at the output signal node according to the combination ofdigital input values at the corresponding input signal nodes.
 10. Themethod of claim 9, wherein the selectively configurable section includesa 2:1 multiplexer.
 11. A circuit for use in multiplexer-implementedlogic, comprising: a plurality of multiplexing stages, each including atleast first and second input nodes adapted to receive input signals, atleast one control node adapted to receive a control signal, and anoutput node adapted to produce an output signal; wherein the pluralityof multiplexing stages are hierarchically arranged so that the outputnode of each multiplexing stage except the final stage is connected tothe first input node of the next higher multiplexing stage; and whereinthe final multiplexing stage is configured so that, if the controlsignal on the control node of the final stage is equivalent to a firstlogic value, then the output signal produced on the output node of thefinal stage is the inverse of the input signal on the first input nodeof the final stage, and if the control signal on the control node of thefinal stage is equivalent to the inverse of the first logic value, thenif the input signal on the second input node of the final stage isequivalent to the inverse of the first logic value, then the outputsignal produced on the output node of the final stage is the first logicvalue, else the output signal produced on the output node of the finalstage is the inverse of the input signal on the first input node of thefinal stage.
 12. The digital logic circuit of claim 11, wherein theplurality of multiplexing stages include a plurality of TGM's arrangedin a serial cascade structure.
 13. The digital logic circuit of claim11, wherein the final multiplexing stage comprises no more than sixtransistors.
 14. The digital logic circuit of claim 13, wherein thefinal multiplexing stage includes CMOS transistors.
 15. The digitallogic circuit of claim 11, wherein the final multiplexing stage isselectively configurable between a first configuration where the firstdigital logic value is a 1, and a second configuration where the firstdigital logic value is a
 0. 16. The digital logic circuit of claim 11,wherein the final multiplexing stage is selectively reconfigurable sothat if the input signal on the second input node of the final stage isequivalent to the first logic value, then the output signal produced onthe output node of the final stage is the inverse of the first logicvalue, else the output signal produced on the output node of the finalstage is the inverse of the input signal on the first input node of thefinal stage.
 17. An electronic circuit for use in digital logic design,comprising: means for selecting one of N input signals; and means,controllable by one or more control signals, for transmitting to anoutput node either an inverse of the selected input signal or an inverseof the one or more control signals.
 18. The circuit of claim 17, whereinthe means for transmitting is selectively configurable between a firstconfiguration where the constant logic value is a 0, and a secondconfiguration where the constant logic value is a
 1. 19. The circuit ofclaim 17, wherein the means for transmitting includes no more than sixtransistors.
 20. The circuit of claim 17, wherein the means forselecting includes a 2:1 multiplexer.
 21. The circuit of claim 17,wherein the means for selecting includes a 3:1 multiplexer.
 22. Thecircuit of claim 17, wherein the means for selecting includes a 4:1multiplexer.
 23. An electronic circuit comprising: a multiplexerconfigured to transmit a selected one of N input signals, wherein themultiplexer includes one or more TGM's arranged in a serial cascadestructure; output means for receiving the signal transmitted by themultiplexer and outputting an inverse of the signal; and control meansfor enabling and disabling the output means in response to one or morecontrol signals.
 24. The circuit of claim 23, wherein the control meansincludes means for outputting a logic signal when the output means isdisabled.
 25. The circuit of claim 24, wherein the control means isselectively configurable to output either a logical 0 or a logical 1.26. The circuit of claim 25, wherein the logic signal is an inverse ofthe one or more control signals.
 27. The circuit of claim 23, whereinthe output means includes an inverter.
 28. The circuit of claim 23,wherein the multiplexer is a 2:1 multiplexer.
 29. The circuit of claim23, wherein the multiplexer is a 3:1 multiplexer.
 30. The circuit ofclaim 24, wherein the multiplexer is a 4:1 multiplexer.
 31. Anelectronic digital function generator comprising: a first sectionincluding a serial cascade TGM multiplexer having an output node andconfigured to transmit one of N input signals to the output nodedepending on N-1 select signals; and a second section including aninverter with an input node and an output node, wherein the input nodeof the inverter is connected to the output node of the first section,and a control circuit with one or more control nodes adapted to receiveone or more digital control signals, wherein the control circuit isconfigured to enable the inverter when the one or more digital controlsignals are in a first state, and wherein the control circuit isconfigured to disable the inverter and connect the output node to atleast one of VDD and Ground when the one or more digital control signalsare in a state different than the first state.
 32. The electronicdigital function generator of claim 31, wherein the first sectioncomprises a 3:1 serial cascade TGM multiplexer.
 33. The electronicdigital function generator of claim 31, wherein the second sectionincludes no more than six transistors.
 34. The electronic digitalfunction generator of claim 33, wherein the second section includes sixCMOS transistors.
 35. The electronic digital function generator of claim31, wherein the control circuit is selectively configurable in either afirst configuration in which the control circuit disables the inverterwhen the digital control signals are all logical 1's, and a secondconfiguration in which the control circuit disables the inverter whenthe digital control signals are all logical 0's.
 36. The electronicdigital function generator of claim 31, wherein the first sectioncomprises a 4:1 serial cascade TGM multiplexer.
 37. A CMOS digitalelectronic circuit comprising: a first section adapted to transmit oneof N input signals; and a second section adapted to receive the signaltransmitted by the first section and two control signals, and to outputeither an inverse of the signal transmitted by the first section or alogical 0, the output being responsive to the two control signals, andwherein the second section includes no more than six transistors. 38.The circuit of claim 37, where the first section is configured withoutfeedback or fan-out, and where the second section is configured withoutfeedback to the first section.
 39. A CMOS digital electronic circuitcomprising: a first section adapted to transmit one of N input signals;and a second section adapted to receive the signal transmitted by thefirst section and two control signals, and to output either an inverseof the signal transmitted by the first section or a logical 1, theoutput being responsive to the two control signals, and wherein thesecond section includes no more than six transistors.
 40. The circuit ofclaim 39, where the first section is configured without feedback orfan-out, and where the second section is configured without feedback tothe first section.